The present invention relates to a position detecting method, and more particularly to a position detecting method used for an alignment for a wafer in a semiconductor exposure apparatus. The present invention is suitable, for example, for a position detecting method used to manufacture various devices including semiconductor chips such as ICs and LSIs, display devices such as liquid crystal panels, sensing devices such as magnetic heads, and image pick-up devices such as CCDs.
Recent high performance and inexpensive electronic apparatuses needs more economic and precise manufacturing of semiconductor installed in them, and requires an exposure apparatus that exposes a semiconductor circuit pattern to have precision and efficiency in a process of transferring a circuit pattern on a reticle or a mask (collectively referred to as a “reticle” hereinafter) onto a wafer and a glass plate (collective referred to as a “wafer” hereinafter), on which a photosensitive material (referred to as “resist” hereinafter) is applied. In general, precise exposure of a circuit pattern requires a precise alignment between the reticle and the wafer.
A conventional alignment method exposes alignment marks on a wafer at the same time when the circuit pattern on the reticle is exposed, and sequentially measures positions of plural preset alignment marks among the alignment marks for all the shots using an alignment detection optical system. After the position measurement result is statistically processed to calculate the entire shot arrangement, and the wafer is positioned to the reticle based on the calculation result.
The alignment marks are indexes to align the reticle with the wafer with high precision. Fine circuit patterns require a precise alignment between a reticle and a wafer; the necessary precision is about ⅓ of a circuit critical dimension, e.g., 60 nm that is ⅓ as long as the current design width of 180 nm. The recently introduced special semiconductor manufacture technology, such as a chemical mechanical polishing (“CMP”) process causes scattering among shapes of the alignment marks among wafers and among shots, and deteriorate the alignment accuracy. Other factors, which result from apparatus's performance, also deteriorate the alignment accuracy, such as inclination errors in the illumination optical system, and a coma. In this case, the process condition varies in the apparatus to set a suitable condition for both the alignment mark and circuit pattern. Plural types of alignment marks with different widths are produced for exposure evaluations, and the alignment mark having a certain is selected for a certain process condition, which is supposed to provide the highest precision.
Prior art relating to a position detecting method includes, for example, Japanese Patent Applications, Publication Nos. 05-062879 and 09-186222.
Optimal conditions for the semiconductor device manufacture process are manually calculated and require a long time. Even after a parameter is determined, it is necessary to manually recalculate and change the manufacture process when the process error occurs.
This modification also requires a long time. Therefore, the conventional alignment process requires an extremely long time, lowering the yield of the semiconductor device manufacturing.
It is predicted that the finer processing of a circuit pattern will be demanded, a new semiconductor process will be introduced, and a wafer diameter will become larger, for example, 300 mm. Accordingly, in addition to a problem of the yield, precise
manufacturing of both the circuit pattern and the alignment mark on the whole wafer surface without defect will become more and more difficult.